Conventional programmable logic devices (PLD's) comprise one or more arrays of logic elements (LE's), and the base signal routing architecture between LE's is designed such that LE-to-LE routing (typically performed by software programs that convert hardware design language program instructions into such routing) is optimized. Examples of PLD's having more than one array include PLD's in the APEX family of devices, by Altera Corporation of San Jose, Calif. It is sometimes desired to add one or more IP function blocks among an LE array. For the purposes of this disclosure, an LE is considered to be a basic—or most common—logic element that functions, for example, with respect to look-up table or macrocell logic. The LE's of an array are nominally connected by a base signal routing architecture. An IP function block is a functional block that is not constrained by the function of the most common logic element. For example, by way of illustration and not by limitation, an IP function block may be a high-speed serial interface (HSSI), a digital signal processor or other microprocessor, ALU, memory, or a multiplier.
Conventionally, when an IP function block is added to an LE array, the IP function block is placed at an edge of the LE array and spanning the entire edge of the LE array. This minimizes the disruption in the base routing. Furthermore, by placing the IP function block at an edge of the array, the performance degradation that would otherwise be caused by routing over the IP function block is minimized. A disadvantage of placing the IP function block at an edge of the LE array, however, is that the input/output (I/O) cells (for communication off the LE array) are conventionally located at the edge of the LE array. The IP function block may not even require access to the I/O cells at that edge but, nonetheless, impedes access by other elements (LE's, or even other IP function block) to the I/O cells at the edge where the IP function block is placed. In some cases, such as is described in U.S. Pat. No. 5,550,782, a block such as an embedded array block (EAB) completely replaces a logic array block (LAB) of LE's. In this case, the routing connects to the EAB in much the same way that the routing interfaces with the conventional logic block and, thus, there is no corresponding performance degradation.
Clearly, placement of an IP function block within an LE array of a PLD has commonly been an afterthought such that, typically, an IP function block was merely placed where it could best fit to minimize the disruption to the base signal routing architecture. What is desired is a PLD architecture by which the placement of an IP function block is not dictated by the goal of minimizing the disruption to the base signal routing architecture.